AK8181G draft - e - 01 feb - 2013 - 1 - features four differential 3.3v lvds outputs selectable two lvcmos/lvttl clock in puts clock output frequency up to 650 mhz translates lvcmos/lvttl input signals to lvds levels o utput skew : 3 0ps ( max imum ) part - to - part skew : 5 0 0ps ( maximum ) propagat ion delay : 2 . 2 ns ( maximum ) add itive phase jitter(rms): 0.1 ps ( typ ical ) operating temperature range: - 4 0 to +85 package: 20 - pin tssop (pb free) pin compatible with ics8545i description the ak 8181 g is a member of akm s lv ds clock fanout buffer family d esigned for telecom, networking and computer applications , requiring a ra nge of clocks with high performance and low skew . the ak 8181 g distributes 4 buffered clocks . ak 8181 g are derived f r o m akm s long - term - experienced clock devic e technology , and enable clock output to perform low skew . the ak 8181 g is ava ilable in a 20 - pin tssop pa ckage. block diagram 3.3v lvds 1: 4 preliminary clock fanout buffer ak 8181 g
AK8181G feb - 2013 draft - e - 01 - 2 - pin d escription s package: 20 - pin tssop(top view) pin no. pin name pin type pullup down description 1 vss pwr --- negative power supply 2 clk_en in pull up synchronizing clock output enable (lvcmos/lvttl) pin is connected to vdd by internal resistor. (typ. 51k ? ? high (open): clock outputs follow clock input. low: q outputs are forced low, qn outputs are forced high. 3 clk_sel in pull dow n clk select input (lvcmos/lvttl) pin is connected to vss by internal resistor. (typ. 51k ? ? high: selects clk 2 input low (open): selects clk 1 input 4 clk 1 in pull down single - ended clock input pin is connected to vss by internal resistor. (typ. 51k ? ? 5 nc -- --- no connect 6 clk 2 in pull down single - ended clock input pin is connected to vss by internal resistor. (typ. 51k ? ? 7 nc -- --- no connect 8 oe in pull up output enable. controls enablin g and disabling of outputs q0, q0 n through q3, q3 n . pin i s connected to vdd by internal resistor. (typ. 51k ? ? 9 vss pwr --- negative power sup ply 10 vdd pwr --- positive power supply 11, 12 q3n, q3 out --- differential clock output (lvds) 13 vss pwr --- negative power supply 14, 15 q2n, q2 out --- different ial clock output (lvds) 16, 17 q1n, q1 out --- differential clock output (lv d s ) 1 8 vdd pwr --- positive power supply 19, 20 q0n, q0 out --- differential clock output (lv ds ) ordering information part number marking shipping packaging package temper ature range ak818 1 g ak 81 81 g tape and reel 20 - pin tssop - 4 0 to 85 c
AK8181G draft - e - 01 feb - 2013 - 3 - absolute maximum rating over operating free - air temperature range unless otherwise noted (1) items s ymbol ratings unit s upply v oltage vdd - 0.3 to 4.6 v input voltage vin vss - 0. 5 to v dd+0. 5 v input c urrent (any pins except supplies) i in 1 0 ma storage temperature tstg - 55 to 15 0 ? c note (1) stress beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only. f unctional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute - maximum - rating conditions for extended periods may affect device reliability. electrical par amete rs are guaranteed only over the recommended operating temperature range. (2) vss=0v this device is manufactured on a cmos process, therefore, generically susceptible to damage by excessive static voltage. failure to observe proper handling and instal lation procedures can cause damage . akm recommends that this device is handled with appropriate precautions. recommended operation condition s parameter s ymbol conditions m in typ m ax unit operating t emperature ta - 4 0 85 ? c supply voltage (1) vdd vd d ? 5% 3. 135 3.3 3. 465 v (1) power of 3.3v requires to be supplied from a single source. a decoupling capacitor of 0.1 ? f for power supply line should be located close to each vdd pin. pin characteristics parameter s ymbol conditions m in typ m ax unit inp ut capacitance c in 4 pf input pullup resistor r pu 51 k input pulldown resistor r pd 51 k p ower supply characteristics parameter s ymbol conditions m in typ m ax unit power supply current i dd clk 1 = input 650mhz clk 2 = open 4 7 ma c lk 1 = open clk 2 = input 650mhz 4 7 ma esd sensitive device
AK8181G feb - 2013 draft - e - 01 - 4 - dc characteristics (lvcmos/lvttl) all specifications at vdd=3.3v ? 5%, ta: - 40 to +85 , unless otherwise noted parameter symbol conditions min typ max unit i nput high v oltage v ih 2.0 vdd+0.3 v i nput low v o ltage clk 1 , clk 2 v il - 0.3 1.3 v clk_sel, oe, clk_en, - 0.3 0.8 v input high c urrent clk_sel i h vin=vdd=3.465v 150 a a l vin=vss, vdd=3.465v - 5 a a dc characteristics (differential) all specifications at vdd=3.3v ? 5%, vss=0v, ta: - 40 to +85 , unless otherwise noted parameter symbol conditions min typ max unit differential output voltage v od 200 280 360 m v v od magnitude change od 40 mv o ffset voltage v os 1.125 1.25 1.375 v v os magnitude change os 5 25 mv high impedance leakage current i oz oe = low - 10 +10 a osd - 3.5 - 5 ma output voltage high v oh 1.34 1.6 v output voltage low v ol 0.9 1.06 v
AK8181G draft - e - 01 feb - 2013 - 5 - ac characteristics all specifications at vdd=3.3v ? 5%, vss=0v, ta: - 40 to +85 , unless otherwise noted all parameters measured at f 650mhz unless noted otherwise. the cycle to cycle jitter on the input will equal the jitter on the output. the part does not add jitter. (1) measured from v dd /2 of the input to the differential output crossing point. (2) defined as skew between outputs at the same supply voltage and with equal load conditions. (3) this parameter is defined in accordance with jedec standard 65. (4) defined as skew between output s on different devices operating at the same supply voltages and with equal load conditions. u sing the same type of inputs on each device, the outputs are measured at the differential cross points. (5) design value. parameter symbol conditions min typ max unit output frequency f out 650 mhz propagation delay (1) t pd 0.7 2.2 n s output skew (2) (3) t sk(o) 30 ps part - to - part skew (3 ) (4) t skpp 5 0 0 ps buffer additive jitter, rms (5) t jit 156.25mhz (12khz C 20mhz) 0. 1 ps output rise/fall time (5 ) t r , t f 20% to 80% @50mhz 1 00 5 00 p s output duty cycle dc out 4 5 5 5 %
AK8181G feb - 2013 draft - e - 01 - 6 - figure 1 3.3v output load test circuit figure 2 differential ou t put level figure 3 output skew figure 4 output rise/fall time figure 5 propagation delay figure 6 output duty / p ulse width/ period figure 7 p art - to - part skew
AK8181G draft - e - 01 feb - 2013 - 7 - figure 8 offset voltage setup figure 9 differential output voltage setup figure 1 0 high impedance leakage figure 1 1 differential output short circuit current setup setup
AK8181G feb - 2013 draft - e - 01 - 8 - function table the following table shows the inputs/outputs clock state configured through the control pins. table 1 : control input function table inputs outputs oe clk_en clk_sel selected source q0:q3 q0n:q3n 1 0 0 (open) clk 1 disabled: low disabled: high 1 0 1 clk 2 disabled: low disabled: high 1 1 (open) 0 (open) clk 1 enabled enabled 1 1 (open) 1 clk 2 enabled enabled 0 don t care don t care --- hi - z hi - z after clk_en switches, the clock outputs are d isabled or enabled following a rising and falling input clock edge as shown in figure 12 . in the active mode, the state of the outputs are a function of the clk1 and clk2 inputs as described in table 2. figure 12 clk_en timing di agram table 2 : clock input function table inputs outputs clk 1/2 q0 : q3 q0n : q3n 0 low high 1 high low
AK8181G draft - e - 01 feb - 2013 - 9 - package information ? mechanical data : 20pin tssop ? marking ? rohs compliance all integrated circuits fo rm asahi kasei m icrodevices corporation (akm) assembled in lead free packages* are fully compliant (*) rohs compliant products from akm are identified with pb free letter indication on product label posted on the anti - shield bag and boxes. a: #1 pin index b: part number c: d ate code ( 7 digits) 1 20 10 11 ak8181 g xxxxx xx a b c 2 0 1 1 1 0 1 0 . 1 0 0 . 0 5 0 . 9 0 0 . 0 5 1 . 1 0 m a x s 4 . 4 0 0 . 1 0 0 . 1 0 s 6 . 5 0 0 . 1 0 6 . 4 0 0 . 1 0 0 . 6 0 . 1 0 0 . 1 5 0 . 0 5 0 . 2 5 0 . 0 5 0 . 6 5 0 8
AK8181G feb - 2013 draft - e - 01 - 10 - important notice ? these products and their specifications are subject to change without notice. when you consider any use or application of these products, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. ? descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products . you are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. akm assumes no responsibility for any losses incurred by you or third parties arisi ng from the use of these information herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akm assumes no responsibility for such use, except for the use approved with the express written consent by representative director of ak m. as used here: note1) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, i n which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. ? it is the responsibility of the buyer or distributor of akm products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all c laims arising from the use of said product in the absence of such notification.
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